The demands for less expensive, smaller, higher performance integrated circuit devices have motivated the development of new techniques for producing more efficient semiconductor devices. While integrated circuit devices are common across many applications including larger electronic systems, such as cars, planes, industrial control systems, the intense demand is in portable electronics, such as cell phones, portable computers, voice recorders, etc.
In the manufacture and assembly of integrated circuits, first, the integrated circuits are formed on semi-conductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability, in that the packaging cost can easily exceed the cost of the integrated circuit chip, and the majority of device failures are packaging oriented.
A key step in the integrated circuit fabrication is packaging the chip in a suitable medium that will protect it in subsequent manufacturing steps and from the environment of its intended application. In the typical packaging process, there are two main steps: wire bonding and encapsulation. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components of the device. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contaminants and to protect the wire bonds and other components from corrosion and mechanical shock.
The packaging of integrated circuits has generally involved attaching an individual chip to a lead frame, where following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. The packaging of integrated circuits has also involved the placement of a chip on a substrate where, following adhesion of the chip to the surface of the substrate and wire bonding, an encapsulant is placed over the chip and the adjacent substrate to seal and protect the chip and other components.
The known integrated circuit packaging techniques have several disadvantages, particularly with regard to the encapsulation step. In the known techniques, the chip is placed on a lead frame or a flat surface of a flexible board and then a molding process is employed to place an encapsulant over the silicon chip. The molding process generally involves two plates that press against the lead frame or board and attached chip and at least one of the plates includes a mold cavity for molding encapsulant over and around the chip.
In addition to the mold cavities, these plates also have intricate conduits for providing the encapsulant to the mold cavity, commonly called main runners, sub runners, and gates. The main runner provides encapsulant to a multitude of mold cavities; the sub runners provide encapsulant to individual mold cavities; and the gates provide a reduced cross-sectional area where, following the completion of the molding process, the cured encapsulant is cut.
The known techniques for molding encapsulant over a chip attached to a lead frame or the surface of a flexible board have several significant shortcomings. Bond wires can be damaged including wire sagging or wire sweeping. Commonly, wire sagging and wire sweeping result from trapped gases such as air under the substrate. Techniques using pre-heating of temperatures up to about two hundred twenty degrees Celsius and pre-heating times up to about thirty seconds have not provided any significant improvement in reducing wire damage.
Despite the advantages of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for improving manufacturing processes and increasing the number of packages meeting manufacturing specifications.
Thus, a need still remains for an integrated circuit package system to provide compatibility with existing packaging technologies and improvement in manufacturing process yield. In view of the increasing demand for improved density of integrated circuits and particularly portable electronic products, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.